May 18th, 2010
Accellera is standardized the verification methodology and gave it name as “Universal Verification methodology” UVM EA 1.0 is now available. Download it from the accellera.
http://www.accellera.org/activities/vip/
It is basically a combination of good features from OVM and VMM and it will compile on all the simulators which supports the standard system verilog. To me it looks like its mostly derived from the mentor/cadence OVM methodology. Cadence has created the uvmworld.org site something very similar to ovmworld site with forum and other resources. Check it out here.
http://www.uvmworld.org/overview.php
Does UVM mean ovm/vmm will die eventually over a period of time ? I guess yes they will disappear over a time once the UVM is stable.
Some more information from the release notes . Looks like its mostly based on OVM .
The UVM is built on the same code base as OVM-2.1.1, with the following
new feature enhancements which are described in greater detail in the
“New Features” section below and any API changes described in the
“API Changes” section.
- All ovm_* symbols converted to uvm_*.
- Enhancements to the OVM callback facility, including a new message
catching facility. These enhancements introduce some minor backward
incompatibilities to the OVM callback facility.
- Enhancements to the OVM objection mechanism. These enhancements
introduce some minor backward incompatibilities to the OVM objection
mechanism.
Posted in Verification | 42 Comments »
March 19th, 2010
Vim is awesome editor if you know its advance features. One of such feature is marking. Its a life save if you are debugging/editing huge files. You can read more about it here :
http://vim.wikia.com/wiki/Using_marks
http://www.linux.com/archive/feed/54159
In Short to remember :
mx : Mark a line with character x
‘x : return to the marked line
Go to the line you want to mark and press mx in the command mode. That line will be marked with the character ‘x’ and now if you want to come back to that line from anywhere in the file press ‘x it will take you back to the same line. Its a life saver for my huge debugs
~njoy vim
Tags: marking, vim
Posted in Uncategorized | 88 Comments »
January 20th, 2010
- When tough time comes… The tough keep going!
- I have not failed. I’ve just found 10,000 ways that won’t work. – Thomas A. Edison
- Think big,Think fast,Think ahead. Ideas are no one’s monopoly. -Dhirubhai Ambani
Posted in Uncategorized | 45 Comments »
April 30th, 2009
We are trying to compile ovm on the vcs and and I came across some code which was giving issue with VCS but it works in modelsim. So here is what the code looks like :
typedef int pint;
typedef pint pnewint[string];
module test;
pnewint aa [string];
initial begin
aa["ss"]["ss"] = 1;
$display (”I am here in test %d \n”, aa["ss"]["ss"]);
end
endmodule
Output :
=====
VSIM 1> run
run
# I am here in test 1
#
After that I tried a direct deceleration test like :
module test;
int aa [string] [string];
initial begin
aa["ss"]["ss"] = 1;
$display (”I am here in test %d \n”, aa["ss"]["ss"]);
end
endmodule
Output :
=====
VSIM 1> run
run
# I am here in test 1
#
So basically the above statements mean that modelsim allow multi dimentional associative array creation. Now the question is does LRM allows it. I guess it does not
.
Tags: modelsim, questasim
Posted in System Verilog | 83 Comments »
April 29th, 2009
Sometimes when you have your object files inside your source directory and you try to do “svn stat”, It gives too verbose information about the gernerated object files with ? sign. You can mark them as ignore in svn using propedit so that next time when you do “svn stat” they wont be compared.
You can do it using :
svn propedit svn:ignore objects/
and in the log file enter ‘*’. With the above command svn will ignore all files inside objects for comparison in svn stat.
Thanks,
Puneet
Posted in Linux | 42 Comments »
March 31st, 2009
Methodologies helps in building the verification environment. But they sucks also. A small mistake takes lots of time to figure out. If you are using OVM and stuck with debugging some wired error, you can increase the OVM verbosity level from the command line to see what exactly is happening inside the OVM macro’s and classes. Pass the below switch with the command line options.
+OVM_VERBOSITY=600
or something like :
vsim +OVM_TESTNAME=mem_bitwalk_test +OVM_VERBOSITY=600 -do run.do -c mem_tb_top
Tags: OVM
Posted in System Verilog | 54 Comments »
March 30th, 2009
Here I will explain how you can compile and simulate vhdl and verlog based design using the VCS. lets take a small example of counter. The dut will be written in vhdl and the testbench we will write in verilog. Then we will instantiate vhdl counter into our verilog testbench and then compile and simulate it.
Here is the code for dut and testbench.
VHDL DUT :
==========
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
Verilog Testbench
=================
module counterTb;
reg clk;
reg reset;
reg enable;
wire [3:0] count;
initial
begin
$monitor ($time, " Count = %d", count);
clk=0;
reset = 1;
enable = 0;
#5
reset = 0;
enable = 1;
end
initial
forever
#5 clk = ~clk;
initial
#1000 $finish;
// initialize vhdl counter module
counter (.clk(clk),.reset(reset),.enable(enable), .count(count));
endmodule
Steps to compile :
* Create directory for the compiled libraries (mkdir compile)
* Setup “synopsys_sim.setup” file and map libraries in it
- Create file synoosys_sim.setup
- Add line : counter_lib : ./compile/
* Compile the libraries
- vhdlan -work counter_lib counter.vhdl
- vlogan +v2k +incdir+./ -work counter_lib countertb.v
* Elobrate the design and generate executable
- vcs counter_lib.counterTb
* Simulate it.
You can create a makefile also to design and elobrate the design. Something like
all : compile sim
counter_lib : counter.vhdl
vhdlan -work counter_lib counter.vhdl
countertb_lib : countertb.v
vlogan +v2k +incdir+./ -work counter_lib countertb.v
compile : countertb_lib counter_lib
sim :
vcs counter_lib.counterTb
Now you just need to say “make”. It will compile and elobrate the design.
synopsys_sim.setup file content
===============================
counter_lib : ./compile/
WORK>DEFAULT
DEFAULT: ./compile/
ASSERT_IGNORE_WARNING=TRUE
ASSERT_IGNORE_FAILURE=TRUE
ASSERT_IGNORE_ERROR=TRUE
Tags: mixed compilation, vcs, Verilog, Vhdl
Posted in Verilog, Vhdl | 68 Comments »
October 15th, 2008
Diffing the files and merging them is one of the very common task we do everyday. Following are few very useful commands to view the diff using vim and merge them using the vimdiff commands instead of copying and pasting from one file to another.
To diff two files using vim :
vimdiff file1 file2
or
vim -d file1 file2
Ofcourse you can use gvim also but I don’t prefer using GVIM.
gvimdiff file1 file2
Commands :
[c : Jump to previous diff
]c : Jump to the next diff
do or :diffget : Diff obtain (get the changes to the current buffer/file from the other buffer)
dp or :diffput : Diff Put (Put the changes from the current buffer/file to the other buffer)
As this being one of very command task I do, I have mapped them to single keys for the easy access.
nmap <F7> [czz
nmap <F8> ]czz
nmap <F2> do
nmap <F3> dp
The zz in the end of the command [c will center at the point of the diff so that we can view the diff clearly.
~Enjoy Vim
Posted in Linux | 102 Comments »
September 9th, 2008
Here is the example. How you can change the seed for a class and generate different pattern with randc.
If you comment the line “obj.srandom(seed)” it will generate the same pattern again after the cycle.
Try compiling it again with commenting above line.
class randctest;
randc bit [1:0] randbit;
task print;
$display(”Rand C = %d”, randbit);
endtask
endclass
program main;
randctest obj;
initial begin
obj = new();
for (int i=0; i<12; i++) begin
if (i % 4 == 0) begin
obj.srandom(236+i);
$display(”==============”);
end
if (obj.randomize()) begin
obj.print();
end
else begin
$display(”Randomization failed \n”);
end
end
end
endprogram : main
Output :
==============
Rand C = 0
Rand C = 1
Rand C = 2
Rand C = 3
==============
Rand C = 2
Rand C = 1
Rand C = 3
Rand C = 0
==============
Rand C = 1
Rand C = 0
Rand C = 2
Rand C = 3
Posted in System Verilog | 9 Comments »
September 5th, 2008
A good thought :
The difference between a smart person and a wise person is that a wise
person knows how not to get into situations that a smart person knows
how to get out of.
Reference Page :
http://simeons.wordpress.com/2008/09/04/smart-entrepreneurs-vs-wise-entrepreneurs/
Page has few more thoughts out of which the last one i don’t agree :
- Be different, not best
- Do less, not more
- Go around a wall, not through it
- It is better to figure out how not to have to solve a problem as opposed to having to solve the problem.
Posted in Randsom Stuff | 44 Comments »