Here I will explain how you can compile and simulate vhdl and verlog based design using the VCS. lets take a small example of counter. The dut will be written in vhdl and the testbench we will write in verilog. Then we will instantiate vhdl counter into our verilog testbench and then compile and simulate it.
Here is the code for dut and testbench.
VHDL DUT :
==========
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port( clk: in std_logic;
reset: in std_logic;
enable: in std_logic;
count: out std_logic_vector(3 downto 0)
);
end counter;
architecture behav of counter is
signal pre_count: std_logic_vector(3 downto 0);
begin
process(clk, enable, reset)
begin
if reset = '1' then
pre_count <= "0000";
elsif (clk='1' and clk'event) then
if enable = '1' then
pre_count <= pre_count + "1";
end if;
end if;
end process;
count <= pre_count;
end behav;
Verilog Testbench
=================
module counterTb;
reg clk;
reg reset;
reg enable;
wire [3:0] count;
initial
begin
$monitor ($time, " Count = %d", count);
clk=0;
reset = 1;
enable = 0;
#5
reset = 0;
enable = 1;
end
initial
forever
#5 clk = ~clk;
initial
#1000 $finish;
// initialize vhdl counter module
counter (.clk(clk),.reset(reset),.enable(enable), .count(count));
endmodule
Steps to compile :
* Create directory for the compiled libraries (mkdir compile)
* Setup “synopsys_sim.setup” file and map libraries in it
- Create file synoosys_sim.setup
- Add line : counter_lib : ./compile/
* Compile the libraries
- vhdlan -work counter_lib counter.vhdl
- vlogan +v2k +incdir+./ -work counter_lib countertb.v
* Elobrate the design and generate executable
- vcs counter_lib.counterTb
* Simulate it.
- ./simv
You can create a makefile also to design and elobrate the design. Something like
all : compile sim
counter_lib : counter.vhdl
vhdlan -work counter_lib counter.vhdl
countertb_lib : countertb.v
vlogan +v2k +incdir+./ -work counter_lib countertb.v
compile : countertb_lib counter_lib
sim :
vcs counter_lib.counterTb
Now you just need to say “make”. It will compile and elobrate the design.
synopsys_sim.setup file content
===============================
counter_lib : ./compile/ WORK>DEFAULT DEFAULT: ./compile/ ASSERT_IGNORE_WARNING=TRUE ASSERT_IGNORE_FAILURE=TRUE ASSERT_IGNORE_ERROR=TRUE
Tags: mixed compilation, vcs, Verilog, Vhdl
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