Archive for the ‘System Verilog’ Category

Multi Dimentional Associative array with modelsim

Thursday, April 30th, 2009

We are trying to compile ovm on the vcs and and I came across some code which was giving issue with VCS but it works in modelsim. So here is what the code looks like :

typedef int pint;
typedef pint pnewint[string];

module test;
pnewint aa [string];
initial begin
aa["ss"]["ss"] = 1;
$display (”I am here in test %d \n”, aa["ss"]["ss"]);
end
endmodule

Output :

=====

VSIM 1> run
run
# I am here in test           1
#

After that I tried a direct deceleration test like :

module test;
int aa [string] [string];
initial begin
aa["ss"]["ss"] = 1;
$display (”I am here in test %d \n”, aa["ss"]["ss"]);
end
endmodule

Output :

=====

VSIM 1> run
run
# I am here in test           1
#

So basically the above statements mean that modelsim allow multi dimentional associative array creation. Now the question is  does LRM allows it.  I guess it does not :( .

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Posted in System Verilog | 1 Comment »

Changing OVM verbosity from command line

Tuesday, March 31st, 2009

Methodologies helps in building the verification environment. But they sucks also.  A small mistake takes lots of time to figure out. If you are using OVM and stuck with debugging some wired error, you can increase the OVM verbosity level from the command line to see what exactly is happening inside the OVM macro’s and classes.  Pass the below switch with the command line options.

+OVM_VERBOSITY=600

or something like :

vsim +OVM_TESTNAME=mem_bitwalk_test +OVM_VERBOSITY=600 -do run.do -c mem_tb_top

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Posted in System Verilog | 1 Comment »

Changing the seed for a class and generting different patterent for randc

Tuesday, September 9th, 2008

Here is the example. How you can change the seed for a class and generate different pattern with randc.
If you comment the line “obj.srandom(seed)” it will generate the same pattern again after the cycle.
Try compiling it again with commenting above line.

class randctest;
randc bit [1:0] randbit;
task print;
$display(”Rand C = %d”, randbit);
endtask
endclass

program main;

randctest obj;

initial begin
obj = new();
for (int i=0; i<12; i++) begin
if (i % 4 == 0) begin
obj.srandom(236+i);
$display(”==============”);
end
if (obj.randomize()) begin
obj.print();
end
else begin
$display(”Randomization failed \n”);
end
end
end
endprogram : main

Output :
==============
Rand C = 0
Rand C = 1
Rand C = 2
Rand C = 3
==============
Rand C = 2
Rand C = 1
Rand C = 3
Rand C = 0
==============
Rand C = 1
Rand C = 0
Rand C = 2
Rand C = 3

Posted in System Verilog | 3 Comments »