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	<title>Functional Verification Blog &#187; System Verilog</title>
	<atom:link href="http://blog.asicguru.com/category/system-verilog/feed/" rel="self" type="application/rss+xml" />
	<link>http://blog.asicguru.com</link>
	<description>A Functional Verification Blog</description>
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		<title>Multi Dimentional Associative array with modelsim</title>
		<link>http://blog.asicguru.com/2009/04/multi-dimentional-associative-array-with-modelsim/</link>
		<comments>http://blog.asicguru.com/2009/04/multi-dimentional-associative-array-with-modelsim/#comments</comments>
		<pubDate>Thu, 30 Apr 2009 13:56:34 +0000</pubDate>
		<dc:creator>Puneet</dc:creator>
				<category><![CDATA[System Verilog]]></category>
		<category><![CDATA[modelsim]]></category>
		<category><![CDATA[questasim]]></category>

		<guid isPermaLink="false">http://asicguru.com/blog/?p=57</guid>
		<description><![CDATA[We are trying to compile ovm on the vcs and and I came across some code which was giving issue with VCS but it works in modelsim. So here is what the code looks like :
typedef int pint;
typedef pint pnewint[string];
module test;
pnewint aa [string];
initial begin
aa["ss"]["ss"] = 1;
$display (&#8221;I am here in test %d \n&#8221;, aa["ss"]["ss"]);
end
endmodule
Output :
=====
VSIM [...]]]></description>
			<content:encoded><![CDATA[<p>We are trying to compile ovm on the vcs and and I came across some code which was giving issue with VCS but it works in modelsim. So here is what the code looks like :</p>
<p>typedef int pint;<br />
typedef pint pnewint[string];</p>
<p>module test;<br />
pnewint aa [string];<br />
initial begin<br />
aa["ss"]["ss"] = 1;<br />
$display (&#8221;I am here in test %d \n&#8221;, aa["ss"]["ss"]);<br />
end<br />
endmodule</p>
<p>Output :</p>
<p>=====</p>
<p>VSIM 1&gt; run<br />
run<br />
# I am here in test           1<br />
#</p>
<p>After that I tried a direct deceleration test like :</p>
<p>module test;<br />
int aa [string] [string];<br />
initial begin<br />
aa["ss"]["ss"] = 1;<br />
$display (&#8221;I am here in test %d \n&#8221;, aa["ss"]["ss"]);<br />
end<br />
endmodule</p>
<p>Output :</p>
<p>=====</p>
<p>VSIM 1&gt; run<br />
run<br />
# I am here in test           1<br />
#</p>
<p>So basically the above statements mean that modelsim allow multi dimentional associative array creation. Now the question is  does LRM allows it.  I guess it does not <img src='http://blog.asicguru.com/wp-includes/images/smilies/icon_sad.gif' alt=':(' class='wp-smiley' /> .</p>
]]></content:encoded>
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		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>Changing OVM verbosity from command line</title>
		<link>http://blog.asicguru.com/2009/03/changing-ovm-verbosity-from-command-line/</link>
		<comments>http://blog.asicguru.com/2009/03/changing-ovm-verbosity-from-command-line/#comments</comments>
		<pubDate>Tue, 31 Mar 2009 07:19:42 +0000</pubDate>
		<dc:creator>Puneet</dc:creator>
				<category><![CDATA[System Verilog]]></category>
		<category><![CDATA[OVM]]></category>

		<guid isPermaLink="false">http://asicguru.com/blog/?p=8</guid>
		<description><![CDATA[Methodologies helps in building the verification environment. But they sucks also.  A small mistake takes lots of time to figure out. If you are using OVM and stuck with debugging some wired error, you can increase the OVM verbosity level from the command line to see what exactly is happening inside the OVM macro&#8217;s and [...]]]></description>
			<content:encoded><![CDATA[<p>Methodologies helps in building the verification environment. But they sucks also.  A small mistake takes lots of time to figure out. If you are using OVM and stuck with debugging some wired error, you can increase the OVM verbosity level from the command line to see what exactly is happening inside the OVM macro&#8217;s and classes.  Pass the below switch with the command line options.</p>
<p>+OVM_VERBOSITY=600</p>
<p>or something like :</p>
<p>vsim +OVM_TESTNAME=mem_bitwalk_test +OVM_VERBOSITY=600 -do run.do -c mem_tb_top</p>
]]></content:encoded>
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		<slash:comments>3</slash:comments>
		</item>
		<item>
		<title>Changing the seed for a class and generting different patterent for randc</title>
		<link>http://blog.asicguru.com/2008/09/changing-the-seed-for-a-class-and-generting-different-patterent-for-randc/</link>
		<comments>http://blog.asicguru.com/2008/09/changing-the-seed-for-a-class-and-generting-different-patterent-for-randc/#comments</comments>
		<pubDate>Tue, 09 Sep 2008 06:56:03 +0000</pubDate>
		<dc:creator>Puneet</dc:creator>
				<category><![CDATA[System Verilog]]></category>

		<guid isPermaLink="false">http://puneetworld.com/archives/45</guid>
		<description><![CDATA[Here is the example. How you can change the seed for a class and generate different pattern with randc.If you comment the line &#8220;obj.srandom(seed)&#8221; it will generate the same pattern again after the cycle. Try compiling it again with commenting above line. 
class randctest;    randc bit [1:0] randbit;    task [...]]]></description>
			<content:encoded><![CDATA[<p>Here is the example. How you can change the seed for a class and generate different pattern with randc.<br />If you comment the line &#8220;obj.srandom(seed)&#8221; it will generate the same pattern again after the cycle. <br />Try compiling it again with commenting above line. </p>
<p>class randctest;<br />    randc bit [1:0] randbit;<br />    task print;<br />        $display(&#8221;Rand C = %d&#8221;, randbit);<br />    endtask<br />endclass</p>
<p>program main;</p>
<p>    randctest obj;</p>
<p>    initial begin<br />        obj = new();<br />        for (int i=0; i&lt;12; i++) begin<br />            if (i % 4 == 0) begin<br />                obj.srandom(236+i);<br />                $display(&#8221;==============&#8221;);<br />            end<br />            if (obj.randomize()) begin<br />                obj.print();<br />            end<br />            else begin<br />                $display(&#8221;Randomization failed \n&#8221;);<br />            end<br />        end<br />    end<br />endprogram : main</p>
<p>Output :<br />==============<br />Rand C = 0<br />Rand C = 1<br />Rand C = 2<br />Rand C = 3<br />==============<br />Rand C = 2<br />Rand C = 1<br />Rand C = 3<br />Rand C = 0<br />==============<br />Rand C = 1<br />Rand C = 0<br />Rand C = 2<br />Rand C = 3</p>
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		<slash:comments>5</slash:comments>
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