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	<title>Functional Verification Blog &#187; OVM</title>
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	<description>A Functional Verification Blog</description>
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		<title>Changing OVM verbosity from command line</title>
		<link>http://blog.asicguru.com/2009/03/changing-ovm-verbosity-from-command-line/</link>
		<comments>http://blog.asicguru.com/2009/03/changing-ovm-verbosity-from-command-line/#comments</comments>
		<pubDate>Tue, 31 Mar 2009 07:19:42 +0000</pubDate>
		<dc:creator>Puneet</dc:creator>
				<category><![CDATA[System Verilog]]></category>
		<category><![CDATA[OVM]]></category>

		<guid isPermaLink="false">http://asicguru.com/blog/?p=8</guid>
		<description><![CDATA[Methodologies helps in building the verification environment. But they sucks also.  A small mistake takes lots of time to figure out. If you are using OVM and stuck with debugging some wired error, you can increase the OVM verbosity level from the command line to see what exactly is happening inside the OVM macro&#8217;s and [...]]]></description>
			<content:encoded><![CDATA[<p>Methodologies helps in building the verification environment. But they sucks also.  A small mistake takes lots of time to figure out. If you are using OVM and stuck with debugging some wired error, you can increase the OVM verbosity level from the command line to see what exactly is happening inside the OVM macro&#8217;s and classes.  Pass the below switch with the command line options.</p>
<p>+OVM_VERBOSITY=600</p>
<p>or something like :</p>
<p>vsim +OVM_TESTNAME=mem_bitwalk_test +OVM_VERBOSITY=600 -do run.do -c mem_tb_top</p>
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